With the increased demand for higher data rate standards, such as Long Term Evolution (LTE) with more than 50 Mbps, and with hardware design processes failing to achieve the speed required to process those rates, conventional hardware designs are increasingly providing an array of processors working in parallel to increase the overall processing speed in order to achieve the required data rate. However, problems associated with this type of design include the use of conventional turbo code interleavers, such as WCDMA rel-6 turbo code interleavers, that were not designed for parallel processing and are not contention free, resulting in significant performance degradation that varies based on the data block size.
Contention-free interleavers, such as permutation interleavers, have been proposed. For example, a duobinary turbo coding interleaver in the 802.16 standard provides an interleaver that is contention-free for 2 or 4 parallel MAP decoders. However, disadvantages of currently available contention-free interleavers include the allowance of only a discrete set of block sizes and the possibility of contentions for more than 4 MAP decoders. Therefore, there is a need in the art for an improved contention-free interleaver that may be used with an array of processors operating in parallel.